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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 41311hkpc 20110318-s00006 no.a1948-1/13 LC749403BG overview LC749403BG is a ic which enables higher picture quality in lcd products by improving the signals outputed to the lcd panel. in addition to the function to improve the picture quality of the color equation and the brightness correction, smooth picture quality is realized by converting one seg video from 15fps to 30fps using flame interpolation technique. it supports up to wvga resolution. * features (1) digital input/output ? supports digital video input: ycbcr/ypbpr 24bit,16bit (4: 2: 2) signals or itu-r bt.656 (8bit) input ? digital rgb 24 bit signal input ? digital rgb 18bit/24bit signal output ? digital ycbcr 16bit/24bit signal output (2) picture quality improvement function ? y signal picture quality improvement: brigntness adjust ment, contour correction,cdex (color depth expander), ? c signal picture quality improvement: color exciter,skin color correction,color and hue adjustment ? rgb signal picture quality improvement: brightness, contrast, white balance, black balance, gamma correction (3) panel interface ? embedded timing controller for panel driver ? automtic timing signal generation for panel protection ? pwm for backlight control (video adaptation low power consumtion processing) (4) frame interpolation ( 2) for one-seg broadcast ? double-speed ( 2) mode (15fps ? 30fps) intermediate image is predicted from the previous and next image. *: video input of the LC749403BG meets the following conditions: (1) horizontal resolution is under 880 dots, and (2) vertical resolution is under 480 lines. cmos ic silicon gate lcd picture quality improvement ic orderin g numbe r : ena1948
LC749403BG no.a1948-2/13 lsi specifications ? power supply voltage (typ) core block: 1.2v sdram i/f block: 1.8v i/o block: 1.8v/2.85v/3.3v selectable ? maximum operating frequency internal: 36mhz sdram i/f block: 80mhz ? package: fbga144 11mm 11mm (stacked mcp with sdram) target application ? lcd display devices, one-seg broadcast receiver (car-n avigation, one-seg tv, po rtable dvd player, etc) frame interpolation ( 2) example smooth image quality is realized by converting one seg video from 15fps to 30fps using flame interpolation technique jumpy motion smooth motion interpolation off (15frame/s) actual image interpolation on (30frame/s) intermediate image is predicted from the previous and next image interpolated image actual image
LC749403BG no.a1948-3/13 cdex (color depth expander) example this specification may be changed without any notices for product improvement. specifications absolute maximum ratings at ta = 25 c, dv ss = 0v, av ss _pll = 0v, av ss _osc = 0v, sdv ss = 0v, sdv ssq = 0v parameter symbol conditions ratings unit maximum supply voltage (i/o) dv dd _io -0.3 to +3.96 v maximum supply voltage (sdram, sdramif i/o, pll) dv dd _sdio, av dd _pll, sdv dd , sdv ddq -0.3 to +2.6 v maximum supply voltage (core, osc) dv dd _core av dd _osc -0.3 to +1.8 v digital input voltage v i -0.3 to dv dd _io+0.3 v digital output voltage v o -0.3 to dv dd _io+0.3 v operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operation ranges at ta = -40 to +85 c, dv ss = 0v, av ss _pll = 0v, av ss _osc = 0v, sdv ss = 0v, sdv ssq = 0v ratings parameter symbol conditions min typ max unit 2.6 2.85 3.6 v supply voltage (i/o) dv dd _io 1.7 1.8 1.95 v supply voltage (sdramif i/o) dv dd _sdio 1.7 1.8 1.95 v supply voltage (sdram, pll) sdv dd , sdv ddq av dd _pll 1.7 1.8 1.95 v supply voltage (core, osc) dv dd _core av dd _osc 1.14 1.2 1.26 v input voltage range v in 0 dv dd _io v original cdex
LC749403BG no.a1948-4/13 dc characteristics at ta = -40 to +85 c, dv ss = 0v, av ss _pll = 0v, av ss _osc = 0v, sdv ss = 0v, sdv ssq = 0v, dv dd _io = 1.7 to 3.6v, dv dd _sdio = 1.7 to 1.95v, dv dd _core = 1.14 to 1.26v, sdv dd = 1.7 to 1.95v, sdv ddq = 1.7 to 1.95v ratings parameter symbol conditions min typ max unit cmos level inputs 0.7dv dd _io v input high-level voltage v ih cmos level schm itt inputs 0.7dv dd _io v cmos level inputs 0.3dv dd _io v input low-level voltage v il cmos level schmit t inputs 0.3dv dd _io v v i =dv dd _io 10 a input high-level current i ih v i =dv dd _io, with pull-down resistor 100 a input low-level current i il v i =dv ss -10 a output high-level voltage v oh cmos voltage: 2.6v to 3.6v, 1.7v to 1.9v i/o type d: i oh = -1ma i/o type e: i oh = -1ma (2ma mode) i oh = -2ma (4ma mode) i/o type f: i oh = -2ma (4ma mode) i oh = -4ma (8ma mode) i/o type g: i oh = -2ma i/o type h: i oh = -1ma (2ma mode) i oh = -2ma (4ma mode) dv dd _io-0.4 v output low-level voltage v ol cmos 0.4 v output leakage current i oz in high-impedance output mode 3 a condition : typ ta = 25 c dv dd _io = 2.85v dv dd _core = 1.2v 98 k pull-down resistance r dn condition : typ ta = 25 c dv dd _io = 1.8v dv dd _core = 1.2v 69 k condition : typ ta = 25 c dv dd _io = 2.85v dv dd _core = 1.2v qvga, tck = 6.6mhz 10step 25 ma operating current drain i ddop condition : typ ta = 25 c dv dd _io = 2.85v dv dd _core = 1.2v wvga, tck = 34.24mhz 10step 112 ma static current drain *1 i ddst condition : typ ta = 25 c dv dd _io = 2.85v dv dd _core = 1.2v output open, v i = dv ss or dv dd _io 35 a *1: certain input pins have build-in pull-down resistors. thus there are cases where, due to the circuit sturucture, the static current drain can not beguranteed.
LC749403BG no.a1948-5/13 package dimensions unit : mm (typ) 3409 pin assignment LC749403BG sanyo : fbga144(11.0x11.0) 1 2 3 4 5 6 7 8 9 10 11 12 m l k j h g f e d c b a 11.0 11.0 1.1 0.8 0.8 1.1 0.4 1.4 max 0.5 side view top view bottom view top view a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 11 12
LC749403BG no.a1948-6/13 block diagram dcrout[7:0] dhso ddeo dcko grst flm oe cpv strb sp dexr pol dygin[7:0] dcbin[7:0] dcrin[7:0] dcbout[7:0] dygout[7:0] mpu LC749403BG osd mix timing controler dhsi dvsi ddei dcki xrst srxd_sda scs_i2sel i2c/sio stxd sck_scl xtali color space convert blcon pwm pwm siosel h/v contour hue fti color exciter color gain w/bl stretch dynamic color space convert white/black balance brightness/contrast rgb pdwn test color depth expander dither osdbl into panel protection dvso lti cti bypass tcon ocillator delay frame interpolation ( 2) sdram controler sdram
LC749403BG no.a1948-7/13 pin functions i/o format pin no. pin symbol i/o format connecting destination remarks a1 av dd _osc p - core voltage analog a2 rc_bias i j resistor analog bias resistor connection (connect this pin to gnd with a 20k ) a3 av ss _osc p - gnd analog a4 dhsi i c cmos digital horizontal synchronizing signal. a5 ddei i c cmos digital data enable signal. connect this pin to gnd in the internal generation mode. a6 stxd o d cmos digital sio data a7 sck_scl i c cmos digital bus clock (common to sio and i 2 c) a8 xtali i c cmos digital panel protection, pwm generation clock connect this pin to gnd when not to be used. a9 test i b cmos digital test (normally, connect this pin to gnd) a10 av dd _pll p - pll voltage analog a11 pdo o j analog test (norma lly, connect this pin to gnd) a12 av ss _pll p - gnd analog b1 dcrin2 i c cmos digital r/cr video. connect this pin to gnd when not to be used. b2 dv dd _core p - core voltage digital b3 dv ss p - gnd digital b4 dv ss p - gnd digital b5 dvsi i c cmos digital vertical synchronizing signal b6 srxd_sda i/o g cmos digital sio data input/i 2 c data input/output b7 xrst i a cmos digital system reset (?l? reset) b8 dcki i c cmos digital video clock. b9 dv dd _sdio p - io voltage digital b10 dv ss p - gnd digital b11 dv ss p - gnd digital b12 dcko o f cmos digital video clock output c1 dcrin1 i c cmos digital r/cr video. connect this pin to gnd when not to be used. c2 dcrin0 i c cmos digital r/cr video. connect this pin to gnd when not to be used. c3 sdv ss p - gnd digital sdram ground c4 sdv ss p - gnd digital sdram ground c5 dv dd _core p - core voltage digital c6 into o d cmos digital interrupt c7 pdwn i a cmos digital ?l? power down connect this pin to gnd when not to be used. c8 siosel i c cmos digital ?l?: i 2 c slave, ?h?: 3 wire sio c9 dv ss p - gnd digital c10 dv ss p - gnd digital c11 dhso/sp2 o e cmos digital horizontal synchronizing signal/start pulse signal for source driver c12 dvso/flm2 o e cmos digital vertical synchr onizing signal/start pulse signal for gate driver continued on next page.
LC749403BG no.a1948-8/13 continued from preceding page. input/output format pin no. pin symbol i/o format connecting destination remarks d1 dcrin3 i c cmos digital r/cr video. connect this pin to gnd when not to be used. d2 dcrin4 i c cmos digital r/cr video. connect this pin to gnd when not to be used. d3 dcrin5 i c cmos digital r/cr video. connect this pin to gnd when not to be used. d4 dv ss p - gnd digital d5 sdv ss p - gnd digital sdram ground d6 sdv ss p - gnd digital sdram ground d7 sdv dd p - io voltage digital sdram power d8 sdv dd p - io voltage digital sdram power d9 pwm o d cmos digital pulse width modulation waveform d10 osdbl i c cmos digital data enable signal for external osd. (connect to gnd when not used.) d11 scs_i2sel i a cmos digital sio chip enable/i 2 c slave select d12 ddeo o e cmos digital data enable signal e1 dcrin7 i c cmos digital r/cr video(msb). connect this pin to gnd when not to be used. e2 dcrin6 i c cmos digital r/cr video. connect this pin to gnd when not to be used. e3 dygin1 i c cmos digital g/y/656 video. con nect this pin to gnd when not to be used. e4 dygin0 i c cmos digital g/y/656 video (lsb). connect this pin to gnd when not to be used. e5 dv dd _io p - io voltage digital e6 dv dd _io p - io voltage digital e7 dv dd _io p - io voltage digital e8 dv dd _core p - core voltage digital e9 dbout4 o e cmos digital b/cb/c video e10 dbout5 o e cmos digital b/cb/c video e11 dbout6 o e cmos digital b/cb/c video e12 dbout7 o e cmos digital b/cb/c video (msb) f1 dygin3 i c cmos digital g/y/656 video. con nect this pin to gnd when not to be used. f2 dygin2 i c cmos digital g/y/656 video. con nect this pin to gnd when not to be used. f3 dygin5 i c cmos digital g/y/656 video. con nect this pin to gnd when not to be used. f4 dygin4 i c cmos digital g/y/656 video. con nect this pin to gnd when not to be used. f5 dv dd _core p - core voltage digital f6 dv dd _core p - core voltage digital f7 dv dd _io p - io voltage digital f8 dv dd _core p - core voltage digital f9 dbout1 o e cmos digital b/cb/c video f10 dbout3 o e cmos digital b/cb/c video f11 dbout0 o e cmos digital b/cb/c video (lsb) f12 dbout2 o e cmos digital b/cb/c video continued on next page.
LC749403BG no.a1948-9/13 continued from preceding page. input/output format pin no. pin symbol i/o format connecting destination remarks g1 dcbin0 i c cmos digital b/cb/c video g2 dygin6 i c cmos digital g/y/656 video g3 dygin7 i c cmos digital g/y/656 video g4 dcbin1 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. g5 dv dd _core p - core voltage digital g6 dv dd _core p - core voltage digital g7 dv dd _sdio p - io voltage digital g8 dv dd _sdio p - io voltage digital g9 dgout5 o e cmos digital g/y/656 video g10 dgout6 o e cmos digital g/y/656 video g11 dgout3 o e cmos digital g/y/656 video g12 dgout7 o e cmos digital g/y/656 video (msb) h1 dcbin4 i c cmos digital b/cb/c video h2 dcbin3 i c cmos digital b/cb/c video h3 dcbin2 i c cmos digital b/cb/c video h4 dcbin5 i c cmos digital b/cb/c video h5 dv dd _sdio p - io voltage digital h6 dv dd _sdio p - io voltage digital h7 dv dd _sdio p - io voltage digital h8 dv dd _sdio p - io voltage digital h9 dgout0 o e cmos digital g/y/656 video (lsb) h10 dgout1 o e cmos digital g/y/656 video h11 dgout2 o e cmos digital g/y/656 video h12 dgout4 o e cmos digital g/y/656 video j1 cpv i/o h cmos digital clock signal for gate driver j2 strb i/o h cmos digital data strobe signal for source driver j3 dexr o e cmos digital video inverse signal output for dtr j4 dv ss p - gnd digital j5 dv ss p - gnd digital j6 dv ss p - gnd digital j7 dv ss p - gnd digital j8 dv ss p - gnd digital j9 dv ss p - gnd digital j10 dv ss p - gnd digital j11 dv ss p - gnd digital j12 drout7 i/o h cmos digital r/cr video (msb) continued on next page.
LC749403BG no.a1948-10/13 continued from preceding page. input/output format pin no. pin symbol i/o format connecting destination remarks k1 flm i/o h cmos digital start pulse signal for gate driver k2 oe i/o h cmos digital output enable signal for gate driver k3 dv ss p - gnd digital k4 dv ss p - gnd digital k5 dv ss p - gnd digital k6 dv ss p - gnd digital k7 dv ss p - gnd digital k8 dv ss p - gnd digital k9 dv ss p - gnd digital k10 dv ss p - gnd digital k11 drout0 i/o h cmos digital r/cr video (lsb) k12 drout6 i/o h cmos digital r/cr video l1 dcbin7 i c cmos digital b/cb/c video (msb). connect this pin to gnd when not to be used. l2 sp i/o h cmos digital start pulse signal for source driver l3 sdv ddq p - io voltage digital sdram power *1 l4 sdv ddq p - io voltage digital sdram power *1 l5 sdv ddq p - io voltage digital sdram power *1 l6 sdv ddq p - io voltage digital sdram power *1 l7 sdv ddq p - io voltage digital sdram power *1 l8 sdv ddq p - io voltage digital sdram power *1 l9 sdv ddq p - io voltage digital sdram power *1 l10 dv ss p - gnd digital l11 drout2 i/o h cmos digital r/cr video l12 drout5 i/o h cmos digital r/cr video m1 dcbin6 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. m2 pol o e cmos digital voltage polarity selection signal for source driver m3 grst i/o h cmos digital reset signal for gate driver m4 sdv ssq p - gnd digital sdram ground *2 m5 sdv ssq p - gnd digital sdram ground *2 m6 sdv ssq p - gnd digital sdram ground *2 m7 sdv ssq p - gnd digital sdram ground *2 m8 sdv ssq p - gnd digital sdram ground *2 m9 sdv ssq p - gnd digital sdram ground *2 m10 drout1 i/o h cmos digital r/cr video m11 drout3 i/o h cmos digital r/cr video m12 drout4 i/o h cmos digital r/cr video *1: we recommend isolated power to be supplied to sdram for improved noise immunity. *2: we recommend isolated ground to be supplied to sdram for improved noise immunity.
LC749403BG no.a1948-11/13 pin circuits in/output form function equival ent circuit application terminal a schmitt trigger cmos input xrst, pdwn, scs_i2sel b cmos input with built-in pull-down resister test c cmos input sck_scl, siosel, dvsi, dhsi, ddei, osdbl, dygin7, dygin6, dy gin5, dygin4, dygin3, dygin2, dy gin1, dygin0, dcbin7, dcbin6, dcbin5, dcbin4, dcbin3, dcbin2, dcbin1, dcbin0, dcrin7, dcrin6, dcrin5, dcrin4, dcrin3, dcrin2, dcrin1, dcrin0 d 2ma 3-state drive cmos output stxd, pwm, into e 2ma/4ma switching 3-state drive cmos output dbout7, dbout6, dbout5, dbout4, dbout3, dbout2, dbout1, dbout0, dgout7, dgout6, dgout5, dgout4, dgout3, dgout2, dgout1, dgout0, dhso/sp2, dvso/flm2, ddeo flm, dexr, pol f 4ma/8ma switching 3-state drive cmos output dcko g 4ma 3-state drive cmos input/output srxd_sda h 2ma/4ma switching 3-state cmos input/output drout7, drout6, drout5, drout4, drout3, drout2, drout1, drout0, grst, cpv, sp, oe, strb j analog input/output rc_bias
LC749403BG no.a1948-12/13 input/output timing (1) input data timing pin name parameter symbol min typ max unit clock cycle t ck 25 ns dcki duty 50 % input data set up time (dv dd _io=2.6 to 3.6v) t su 3 ns input data set up time (dv dd _io=1.7 to 1.95v) t su 3 ns input data hold time (dv dd _io=2.6 to 3.6v) t hd 2 ns dcrin*, dygin*, dcbin*, dvsi, dhsi, ddei, osdbl input data hold time (dv dd _io=1.7 to 1.95v) t hd 2 ns *: we recommend a 50% duty cycle for the input clock. (2) output data timing pin name parameter symbol min typ max unit clock cycle t ck 25 ns dcko duty 50 % output data delay time (dv dd _io=2.6 to 3.6v) i/o typ e: 4ma setting i/o typ f: 8ma setting t ac -3 3 ns output data delay time (dv dd _io=2.6 to 3.6v) i/o typ e: 2ma setting i/o typ f: 4ma setting t ac -3 6 ns output data hold time (dv dd _io=1.7 to 1.95v) i/o typ e: 4ma setting i/o typ f: 8ma setting t ac -5 4 ns drout*, dgout*, dbout*, dvso, dhso, ddeo, dexr, pol, sp, strb, cpv, oe, flm, grst output data hold time (dv dd _io=1.7 to 1.95v) i/o typ e: 2ma setting i/o typ f: 4ma setting t ac -6 9 ns *: when dcko is set to the forward rotation output. output load capacity: 5pf dcko output data t ac t lo t ho t ck dv dd _io/2 dv dd _io/2 t su dcki input data t hd t li t hi t ck dv dd _io/2 dv dd _io/2
LC749403BG ps no.a1948-13/13 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of april, 2011. specifications and information herein are subject to change without notice.

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